/*******************************************************************************
 *                                    ZLG
 *                         ----------------------------
 *                         innovating embedded platform
 *
 * Copyright (c) 2001-present Guangzhou ZHIYUAN Electronics Co., Ltd.
 * All rights reserved.
 *
 * Contact information:
 * web site:    https://www.zlg.cn
 *******************************************************************************/
#ifndef __HPM6E00_REGS_PCFG_H
#define __HPM6E00_REGS_PCFG_H

#ifdef __cplusplus
extern "C" {
#endif  /* __cplusplus*/
#include "core/include/hpm6e00_regs_base.h"
#include <stdint.h>

#define PCFG_LDO2P5_ENABLE_MASK   (1 << PCFG_LDO2P5_ENABLE_POS)
#define PCFG_LDO2P5_ENABLE_POS    (16U)
#define PCFG_LDO2P5_VOLT_MASK     (0xFFFU)
#define PCFG_LDO2P5_VOLT_POS      (0U)

#define PCFG_DCDC_MODE_VOLT_MASK  (0xFFFU)
#define PCFG_DCDC_MODE_VOLT_POS   (0U)

typedef struct {
    volatile uint32_t       BANDGAP;                     /* 0x0: BANGGAP control */
    volatile uint32_t       LDO1P1;                      /* 0x4: 1V LDO config */
    volatile uint32_t       LDO2P5;                      /* 0x8: 2.5V LDO config */
    volatile const uint8_t  RESERVED0[4];                /* 0xC - 0xF: Reserved */
    volatile uint32_t       DCDC_MODE;                   /* 0x10: DCDC mode select */
    volatile uint32_t       DCDC_LPMODE;                 /* 0x14: DCDC low power mode */
    volatile uint32_t       DCDC_PROT;                   /* 0x18: DCDC protection */
    volatile uint32_t       DCDC_CURRENT;                /* 0x1C: DCDC current estimation */
    volatile uint32_t       DCDC_ADVMODE;                /* 0x20: DCDC advance setting */
    volatile uint32_t       DCDC_ADVPARAM;               /* 0x24: DCDC advance parameter */
    volatile uint32_t       DCDC_MISC;                   /* 0x28: DCDC misc parameter */
    volatile uint32_t       DCDC_DEBUG;                  /* 0x2C: DCDC Debug */
    volatile uint32_t       DCDC_START_TIME;             /* 0x30: DCDC ramp time */
    volatile uint32_t       DCDC_RESUME_TIME;            /* 0x34: DCDC resume time */
    volatile const uint8_t  RESERVED1[8];                /* 0x38 - 0x3F: Reserved */
    volatile uint32_t       POWER_TRAP;                  /* 0x40: SOC power trap */
    volatile uint32_t       WAKE_CAUSE;                  /* 0x44: Wake up source */
    volatile uint32_t       WAKE_MASK;                   /* 0x48: Wake up mask */
    volatile uint32_t       SCG_CTRL;                    /* 0x4C: Clock gate control in PMIC */
    volatile const uint8_t  RESERVED2[16];               /* 0x50 - 0x5F: Reserved */
    volatile uint32_t       RC24M;                       /* 0x60: RC 24M config */
    volatile uint32_t       RC24M_TRACK;                 /* 0x64: RC 24M track mode */
    volatile uint32_t       TRACK_TARGET;                /* 0x68: RC 24M track target */
    volatile const uint32_t STATUS;                      /* 0x6C: RC 24M track status */
} hpm_pcfg_reg_t;

#define HPM_PCFG  ((hpm_pcfg_reg_t *)HPM_PCFG_BASE)

#ifdef __cplusplus
}
#endif  /* __cplusplus  */
#endif




